The present invention relates generally to the field of heat processing a treatment object such as, for example, a semiconductor substrate, and, more particularly to a process chamber having a selective reflectivity profile for use in such heat processing.
Thermal processing of treatment objects such as, for example, semiconductor substrates, usually requires initially ramping the substrate temperature to a high temperature in a process chamber so that a process can be performed at high temperature. In a so-called “soak” process, the substrate is left at a given process temperature for a specified period of time and is then ramped down in temperature for unloading from the process chamber.
Typical processes include annealing of ion-implantation damage, silicide formation, oxidation, film deposition and densification or reflow of deposited films. In some processes, it is desirable to minimize the time at the high temperature. This can be achieved with what is generally referred to in the art as a “spike” or ultra-shallow junction (USJ) process, wherein the substrate is ramped up to a specified temperature and then is immediately allowed to cool-down. This kind of process has been found to be very useful for annealing ion-implantation damage that is associated with an implanted dopant. That is, the heat treatment serves to maximize electrical activation of the implanted species, as one objective, while minimizing dopant diffusion, as another objective. It is generally accepted in the prior art that these objectives comprise competing interests and that the spike anneal process appears to provide the best-known compromise with respect to optimizing both of these competing objectives. As an example, ultra-shallow p-n junctions can be formed through the combination of low-energy ion implantation with spike anneals. The junctions have the desirable properties of shallow junction depths (typically <˜40 nm) as a result of the minimal time at temperature and low sheet resistances (typically <800 Ω/sq.) as a result of the high temperature used to activate the dopants.
The characteristics of the spike process are sometimes described in terms of the peak temperature and the width of the spike, often specified by the time spent above a threshold temperature defined by (peak temperature−ΔT° C), where ΔT is usually set as 50, 100 or 200° C. Sometimes the process is also characterized by a ramp-up rate and a cool-down rate. It is evident that the ramping and cooling rates will typically affect the peak width of the spike process. Successful spike annealing, that gives the shallowest junctions with the lowest sheet resistances, often requires higher peak temperatures and narrower peak widths. This is especially important for formation of junctions using boron doping, where significant benefits can be gained through spike anneals. A typical spike process can have a peak temperature of 1050° C. and a peak width of approximately 1.7 s for ΔT=50° C.
It is submitted that future device technologies will require further reductions in junction depth and sheet resistance and, hence, it is clear that improved RTP spike processes will be needed. The expected trend is that new processes will mandate a higher process temperature that is accompanied by a narrower peak width The present invention describes a highly advantageous approach in implementing such a new process, while providing still further advantages.
Temperature measurements in RTP systems, such as described above, are critical with respect to process monitoring and control. When radiation pyrometers are used to measure, for example, wafer temperature, the wafer is observed by the pyrometer through an aperture in the process chamber wall. In some cases, it can be useful to make this chamber wall highly reflecting at the pyrometer wavelength, because this condition tends to increase the effective emissivity of the wafer at the pyrometer wavelength. This effect makes the emission of the wafer more closely resemble that of a blackbody radiator. As a result, the pyrometer readings are less sensitive to temperature measurement errors that arise from inadequate knowledge of the wafer's spectral emissivity at the pyrometer wavelength. This is a well-known principle for reducing temperature measurement errors in pyrometry. Unfortunately, accommodating this emissivity characteristic, relating to pyrometry, may adversely influence other important aspects of RTP system operation. The present invention is considered to resolve this difficulty, as will be described below, while providing still further advantages.